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IXARC POWERLINK Rotary Encoders

POSITAL - FRABA Inc.

The generation of POWERLINK encoder is based on a FPGA solution. Thus, the same design has been achieved at almost the same cost as the Fieldbus design.

Cycle times can be up to 400 µs or reach with a low asynchronous data traffic up to 240 µs. Besides the classical polling mode, in which the master (Managing Node) polls each slave (Controlled Node), the POSITAL encoders support the modes "Poll response chaining" and "Poll multiplexing". This expansion of the operating modes allows the customers to implement the new interface design efficient to custom applications in time-critical areas and increase the bandwidth significantly. The encoder profile DS-406 CANopen has been ported to Powerlink.


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